Nonvolatile memory

ABSTRACT

High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source  1  and a drain  2  to change a gate voltage, a current discretely flows between the source  1  and the drain  2  in accordance with quantized electrostatic energy levels in an island electrode  3 . The switching ON/OFF of the current between the source  1  and the drain  2  in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer  6 , its electric field is applied to the island electrode  3 . The current between the source  1  and the drain  2  in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer  6 , and stored data can be held even if power supply is cut off.

TECHNICAL FIELD

The present invention relates to a non-volatile memory, and moreparticularly to a single electron transistor memory, which uses aferroelectric layer for a gate portion.

BACKGROUND OF THE INVENTION

FIG. 8 shows in section the structure of a conventional single electrontransistor memory. Specifically, FIG. 8 shows one of the examples of thesuccessful use of a single electron transistor as a non-volatile memorydevice, which is constructed in a manner that a floating electrode 81 isdisposed on the plane of a substrate between the single electrontransistor and its gate (see Appl. Phys. Lett. 71, 2038, 1997, by Chenet al., Appl. Phys. Lett. 68, 1377 (1996) by S. Tiwari et al., and Tech.Dig. Int. Electron Devices Meet., 541 (1993) by L. Guo et al.). Such amemory operates reading/writing by using the electron emission ofFowler-Nordheim type (FN). Its structure is characterized by easystorage of data even at the high temperature of the memory.

For the writing operation, first, a voltage between a source 1 and adrain 2 is et at 0, then a voltage is applied to a gate electrode 7, andF/N electron emission is started when a predetermined voltage or higheris reached. Accordingly, a gate electric field is generated between thefloating electrode 81 and an island electrode 3, and a current betweenthe source 1 and the drain 2 is controlled. For the reading operation,first, electrons are tunneled through insulating layers 4 and 5 when abias voltage is applied between the source 1 and the drain 2, and storedin the island electrode 3. By measuring a current between the source 1and drain 2 at this time, stored information can be read with highsensitivity, due to single electron tunneling through quantized energylevels in the island.

SUMMARY OF THE INVENTION

However, the FN electron emission needs a relatively high electric fieldintensity because of the tunneling of electrons through a barrier layerbetween the gate and the floating electrode. Consequently, powerconsumption is increased, and deterioration inevitably occurs because ofelectric field stress applied on the barrier layer, thereby putting alimit on the number of rewriting times. In addition, conventionally, arelatively large resistance component has placed a limit on a responsespeed (about ms). In other words, since the conventional single electronmemory is operated by tunneling the electrons through the gateinsulating film, it has been difficult to achieve high devicereliability, reduce power consumption, attain a high operation speed,and so on.

The object of the present invention is to achieve high devicereliability, reduce power consumption, and attain a high-speed operationby realizing a device operation, which prevent the tunneling phenomenonof electrons through a gate insulating film by using a ferroelectriclayer for a gate portion.

More specifically, the objects of the invention are as follows.

To realize a high-speed operation at the polarization response of anatomic order, by using the polarization of the ferroelectric layer asmemory writing/erasing means.

To realize an operation using a very small amount of electrons andconsuming lower power, by using a single electron transistor for readingelectrons.

To provide high durability (mainly decided by the durability of theferroelectric layer) and greatly reduce a device size, by eliminatingthe necessity of electrons tunneling through a gate insulating film.

To facilitate and simplify a manufacturing process compared with an Siferroelectric memory process, by using an established semiconductormanufacturing method (3-layer resist and 3-angle aluminum (Al)deposition (see Jpn. J. Appl. Phys. 35, 1465 (1996) by Y. Nakamura etal.), or the like) so as to eliminate the necessity of precise controlof an insulating film (thickness/horizontal direction), preventing thequality of a deposited Al electrode from being affected from its layeredsurface.

To screen the increase of a gate capacity caused by a high dielectricconstant of a ferroelectric film, by providing a Low-k layer (SiO₂) as agate layer structure.

To enhance the flatness/crystallinity of a ferroelectric layer by usingferroelectric layer growth on a lower gate metal electrode.

To prevent the thermal diffusion of a ferrorlectric component to Si inthe heat treatment process of the ferroelectric layer by providing adiffusion barrier layer.

To increase the degree of device integration by employing a layeredstructure.

According to the invention, to achieve the above-noted objects, mainly aferroelectric layer is used for the electron storage portion of anon-volatile memory (especially, single electron transistor memory). Inthe non-volatile memory, if a ferrorlectric material is used for acapacitor portion, a writing operation is carried out by a polarizationswitch. Accordingly, an operation speed becomes very high (severalnanoseconds). Moreover, since no high electric fields are necessary forthe tunneling of electrons through the barrier layer, the use of theferroelectric material is very advantageous for reducing powerconsumption and enhancing durability.

In accordance with a first means for solution of the invention, anon-volatile memory is provided, comprising:

a gate;

a ferroelectric layer disposed on the gate; and

an island electrode disposed on the ferroelectric layer, held

between a source and a drain by interpolating insulating layers

between the island and each of the source and the drain, andelectrically connected to the gate.

In accordance with a second means for solution of the invention, anon-volatile memory is provided, comprising:

a gate;

a ferroelectric layer disposed on the gate;

a Low-k layer disposed on the ferroelectric layer; and

an island electrode disposed on the Low-k layer, held between a sourceand a drain by interpolating insulating layers between the islandelectrode and each of the source and the drain, and electricallyconnected to the gate.

In accordance with a third means for solution of the invention, anon-volatile memory is provided, comprising:

a gate;

a ferroelectric layer disposed on the gate;

an upper gate disposed on the ferroelectric layer;

a Low-k layer disposed on the ferroelectric layer;

an island electrode disposed on the Low-k layer, held between a sourceand a drain by interpolating insulating layers between the islandelectrode and each of the source and the drain, and electricallyconnected to the gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view illustrating an operation principle of aferroelectric single electron transistor memory according to theinvention.

FIG. 2 is a sectional view of a ferroelectric single electron transistormemory according to a first embodiment of the invention.

FIG. 3 is a view showing an equivalent circuit of the ferroelectricsingle electron transistor memory according to the first embodiment ofthe invention.

FIG. 4 is a sectional view of a ferroelectric single electron transistormemory according to a second embodiment of the invention.

FIG. 5 is a sectional view of a ferroelectric single electron transistormemory according to a third embodiment of the invention.

FIG. 6 is a view showing an equivalent circuit of the ferroelectricsingle electron transistor memory according to the second or thirdembodiment of the invention.

FIG. 7 is a view showing a current/voltage characteristic of theferroelectric single electron transistor memory according to theinvention.

FIG. 8 is a sectional view showing a structure of a conventional singleelectron transistor memory.

DESCRIPTION OF THE PREFERED EMBODYMENT (1) Basic Constitution of theInvention

FIG. 1 is sectional view illustrating the operation principle of aferroelectric single electron transistor memory according to theinvention. This device comprises a source 1, a drain 2, an islandelectrode 3, insulating layers 4 and 5, a ferroelectric layer 6, a gate7 and a substrate 8.

When a predetermined bias voltage is applied between the source 1 andthe drain 2 (to change a gate voltage), a current discretely flowsbetween the source 1 and the drain 2 in accordance with quantizedelectrostatic energy levels in the island electrode 3 having a size ofseveral 10 nm or lower. The switching ON/OFF of the current between thesource 1 and the drain 2 in this case can be carried out by applying½-electron charge (referred to as e/2, hereinafter) to the gate 7. Asingle electron transistor has high current sensitivity. When the gatevoltage induces polarization in the ferroelectric layer 6, its electricfield is applied to the island electrode 3. The current between thesource 1 and the drain 2 in this case can be measured with highsensitivity by the operation of the single electron. Charge holding canbe carried out by the polarization in the ferroelectric layer 6, and theretention can be held even if a power supply is cut off. In addition,the polarization direction of the ferroelectric layer 6 can bedetermined based on the size of the current between the source 1 and thedrain 2.

(2) First Embodiment

FIG. 2 is a sectional view of a ferroelectric single electron transistormemory according to the first embodiment of the invention. This memorycomprises: a diffusion barrier layer 10 formed on the substrate 8; thegate 7 formed on the diffusion barrier layer 10; the ferroelectric layer6 formed on the gate 7 and the diffusion barrier layer 10; the source 1and the drain 2 formed on the ferroelectric layer 6; an island electrode3 formed between the source 1 and the drain 2; the insulating layer 4between the island electrode 3 and the source 1; and the insulatinglayer 5 between the island electrode 3 and the drain 2.

The island electrode 3, the source 1 and the drain 2 can be made of,e.g., Al or Ti. Each of the source 1 and the drain 2 can be made of,e.g., metal having a width and a thickness of about several ten nm. Theisland electrode 3 can be formed to have size of, e.g., several ten nmor lower. The insulating layers 4 and 5 can be made of, e.g., Al oxideor Ti oxide. The island electrode 3, the source 1, and the drain 2,which are made of Al and constitute the single electron transistor, areformed on the same plane. The ferroelectric layer 6 can be made of oneselected from, e.g., PbTiO₃, PbZr_(x)Ti_(1−x)O₃, (Pb, Sr) TiO₃,(Pb_(1−y)Sr_(y)) (Ti_(1−x)) Zr_(x)O₃, SrBi₂Ta₂O₉ BaTiO₃, Bi₃Ti₄O₁₂,LiNbO₃, SrBi₂Ta_(x)Nb_(1−x)O₉. The ferroelectric layer 6 has, forexample, a dielectric constant ∈>100. In this example, the ferroelectriclayer 6 is brought into contact with the areas of the island electrode3, the source 1 and the drain 2, and with the gate 7 and the diffusionbarrier layer 10 around the gate 7.

The gate 7 is made of, e.g., Pt or PhO_(x), disposed below theferroelectric layer 6, and controls the entry/exit of electronsinto/from the island electrode 3. The gate 7 can have a thickness setsubstantially equal to 50 nm or lower. The gate 7 is disposed on thediffusion barrier layer 10 formed on the substrate. When a gatepotential is applied, charges are also stored in the island electrode 3by the gate potential. Thus, a normal single electron transistor can beprovided with another gate for canceling such induced charges. Thediffusion barrier layer 10 can be made of, e.g., TiO_(x) having athickness set substantially equal to 20 nm or higher.

FIG. 3 shows the equivalent circuit of the ferroelectric single electrontransistor according to the first embodiment of the invention. As a gatevoltage is directly applied to the ferroelectric layer 6, a thickness ofthe gate layer is decided under the following conditions, by consideringonly the ferroelectric layer 6.

(a) A gate voltage V_(g) applied through the ferroelectric layer 6should exceed a minimum potential necessary for polarization inside aferroelectric layer. In the described case, this minimum potential isestimated by assuming that a coercive electric field of theferroelectric layer is (E_(c))=50 kV/cm. A condition for this is asfollows:

V _(g) >E _(c)×thickness (d _(g))

From the thickness d_(g), a minimum necessary value of V_(g) is given bythe product of E_(c) and d_(g), If only this condition applies, a gatevoltage is lowered by reducing the thickness as much as possible, makingit possible to reduce power consumption. However, consideration must begiven to the following condition in the device process.

(b) Because of limitations on thin film growth, a minimum thicknessshould be set as follows:

d _(g)>1000 Å (e.g., in the case of PbTiO₃ or PbZr_(x)Ti_(1−x)O₃)

d _(g)>2000 Å (e.g., in the case of SrBi₂Ta₂O₉=SBT)

Thus, gate voltages to be expected are low potentials of, i.e., 0.5 Vwith 1000 Å, and 1.0 V with 2000 Å. However, in the describedembodiment, a gate capacitance is increased, e.g., C_(g)˜1300 aF in thecase of PbTiO₃ (∈˜500), and C_(g)˜500 aF in the case of SBT (∈˜200). Itis larger by 3 digits or more compared with the gate capacitance ˜10⁻¹aF or lower of the conventional metal contacted single electrontransistor (see Jpn. J. Appl. Phys. 35, L1465, 1996, by Nakamura etal.). An operation limit temperature of the single electron transistoris obtained by the, following:

kT=e ²/2C

Accordingly, with the above gate capacitance, an operation temperatureof mK or lower is necessary for the reading operation of the singleelectron transistor. (The symbol ‘˜’ means the symbol ‘≈’.)

(3) Second Embodiment

FIG. 4 is a sectional view showing a ferrorlectric single electrontransistor memory according to the second embodiment of the invention.This memory comprises: the diffusion barrier layer 10 formed on thesubstrate; a gate 7 formed on the diffusion barrier layer 10; theferroelectric layer 6 formed on the gate and the diffusion barrier layer10; a Low-k layer 12 formed on the ferroelectric layer 6; the source 1and the drain 2 formed on the Low-k layer 12; the island electrode 3formed between the source 1 and the drain 2; the insulating layer 4between the island electrode 3 and the source. 1; and the insulatinglayer 5 between the island electrode 3 and the drain 2.

The Low-k layer 12 can be made of, e.g., SiO₂ or Si₃N₄. The role of theLow-k layer 12 (e.g., SiO₂ of ∈˜4) is to screen the increase of the gatecapacitance caused by a high dielectric constant of the ferroelectricfilm, reduce a capacity component due to the line of electric filedsleaked from the island electrode 3 as much as possible and prevent areduction in the operation limit temperature of (kT=e²/2C) of the singleelectron transistor. Other components are similar to those of the firstembodiment.

Generally, grains of micron size are easily generated in a ferroelectriclayer. On the other hand, single crystallization easily occurs on a flatmetal film. If step coverage is present on the substrate in theformation of the ferroelectric layer as shown in FIG. 4, because ofthese characteristics, grains may be generated only on the gate metalelectrode by single crystallization, and a layer showing noferroelectric characteristic may be formed on the diffusion barrierlayer other than the gate metal electrode due to pyrochlore phasecrystallization. Thus, since only the grain portion of the ferroelectriclayer on the gate metal electrode is subjected to polarization, whenintegration can be carried out, adjacent devices can be separated in asize of the gate metal electrode as a device unit, thereby enablingscale down and integration.

(4) Third Embodiment

FIG. 5 is a sectional view showing a ferroelectric single transistormemory according to the third embodiment of the invention. This memorycomprises: the diffusion barrier layer formed on a substrate; a lowergate metal electrode 14 formed on the diffusion barrier layer 10; theferroelectric layer 6 formed on the lower gate metal electrode 14 andthe diffusion barrier layer 10; the Low-k layer 12 formed on theferroelectric layer 6; an upper gate metal electrode 15 formed on theferroelectric layer 6; the source 1 and the drain 2 formed on the Low-klayer 12; the island electrode 3 formed between the source 1 and thedrain 2; the insulating layer 4 between the island electrode 3 and thesource 1; and the insulating layer 5 between the island electrode 3 andthe drain 2.

A difference from the second embodiment is that the upper and lower gatemetal electrodes 15 and 14 made of Pt or the like are disposed on andbelow the ferroelectric layer 6 respectively. The role of the Low-klayer 12 (e.g., SiO₂ of ∈˜4) is to screen the increase of a gatecapacity caused by a high dielectric constant of the ferroelectric film,reduce a capacity component due to the line of electric force leakedfrom the island electrode 3 as much as possible, and prevent a reductionin the operation limit temperature (kT=e²/2C) of the single electrontransistor. In addition, the ferroelectric layer 6 includes a perovskitephase portion 61 and a pyrochlore phase portion 62.

According to the second embodiment, a single crystal grain on the lowergate electrode is correlated to one single electron transistor device,and a writing operation is performed by inducing polarization in theferroelectric layer only by the lower gate electrode. In practice,however, it is not always easy to control the shape of a grain size onlybased on the shape of the lower gate electrode, and variance occurs inthe grain size and a boundary of the grains. Consequently, a writingerror may occur because of an ununiform electric field distributionduring writing. Therefore, according to the third embodiment, in orderto more effectively specify the area of storing electrons directly belowan optional single electron transistor device, the upper gate metalelectrode 15 is newly added, only the perovskite phase portion 61 of theferroelectric layer 6 held between the upper and lower gate metalelectrodes 15 and 14 is subjected to polarization, and then a writingoperation is carried out. As a result, even if the ferroelectric grainsize or its boundary is slightly changed, an electric field distributioncan be more concentrated, and polarization limited to the area directlybelow the single electron transistor can be induced more accurately.Thus, it is possible to further enhance device separation, and suppressan erroneous operation when integration is carried out.

(5) Method for Deciding Thickness and Material for Gate Layer

A material to be selected and a thickness to be set for theferroelectric layer 6 should be decided based on the followingconsideration for both second and third embodiments.

FIG. 6 shows the equivalent circuit of the ferroelectric single electrontransistor memory according to each of the second and third embodiments.In other words, FIG. 6 shows the equivalent circuit shown in each ofFIGS. 4 and 5. Here, a capacity between each electrode of the source 1and the drain 2 and a ground is ignored, and only a gate capacity isconsidered. The equivalent circuit is characterized in that two seriescapacitors (C₁, C₂) are provided between the gate 7 and the islandelectrode 3. Conditions for deciding thickness (d₁, d₂) are describedbelow.

(a) In a gate voltage V_(g) (=V₁+V₂) applied through the capacitors C₁and C₂, V₂ should exceed a minimum potential necessary for polarizationin the ferroelectric layer 6. In the described case, this minimumpotential is estimated by assuming that a coercive electric field of theferroelectric layer is (E_(c))=50 kV/cm. A condition for this is asfollows:

V ₂ >E _(c)×thickness (d ₂)

From the thickness (d₂), a minimum necessary value of V₂ is given byE_(c)d₂.

(b) Because of limitations on thin film growth, a minimum thicknessshould be set as follows:

d ₂>1000 Å (in the case of PbTiO₃ or PbZr_(x)Ti_(1−x)O₃)

d ₂>2000 Å (in the case of SrBi₂Ta₂O₉=SBT)

d ₁>100 Å (equal to/higher than natural oxidized film thickness of SiO₂)

Under these conditions, a combination of d₁ and d₂ for setting V₁+V₂ tobe minimum is discovered. A gate voltage V_(g) is as follows:

V _(g) =V ₁ +V ₂ =V ₂(V ₁ /V ₂+1)

Accordingly, calculation can be made based on V₂ given by the condition(a) and V₁/V₂ provided by the ratio of C₁ to C₂. From the dielectricconstant and the thickness of each of C₁ and C₂, the following results:

V _(g) =E _(c) d ₂(∈₂ d ₂/∈₁ d ₁+1)=E _(c)(∈₂ d ₁/∈₁ +d ₂)  (1)

In this case, d₁ and d₂ are selected based on the size of contributionto V_(g) in the expression (1). From the size relation of dielectricconstants (∈₂>>E₁), (first term)>>(second term) is established inpractice, and thus the contribution of d₁ is large. Thus, it is onlynecessary to reduce d₁. However, there is a limit to such a reductionbecause of a limitation imposed by the condition (b). When a practicalcombination of d₁, and d₂ is selected under the condition (b),conditions for setting V_(g) obtained from the expression (1) beingequal to/lower than 10 V as a practically proper range are as follows:

In the case of PbTiO_(x)(∈₂˜500), V_(g)=6.8 V with d₁=100 Å and d₂=1000Å

In the case of SBT (∈₁˜200), V_(g)=6.0 V with d₁=200 ∈ and d₂=2000 Å

Under the foregoing thickness conditions, as rough estimation made whenthe island electrode 3 is assumed to be a point-charge, a gatecapacitance of the island electrode 3 of the single electron transistoris 0.2 aF, charges stored during the coercive electric field applicationof the ferroelectric layer 6 are ˜1.2 aC (=8e, in the case of SBT), and˜1.4 aC (=9e, in the case of PbTiO_(x)), and induced polarizations are0.4 μC/cm² (in the case of SBT), and 0.5 μC/cm² (in the case ofPbTiO_(x)). Thus, these values are not so deviated from those of theconventional single electron transistor (see Appl. Phys. Lett. 71, 2038,1977 by Chen et al., or Jpn. J. Appl. Phys. 35, L 1465, 1996 by Nakamuraand et al.) and the characteristics of the ferroelectric layer (see OYOBUTSURI, Vol. 67, No. 11, 1257, 1998 by Yasuhiro Umemoto, or Jpn. J.Appl. Phys. 34, 5233, 1995 by Mihara et al.), and are in a sufficientlyoperable range.

(6) Operation

Now, the memory operation of the device structure decided in theforegoing manner will be described. FIG. 7 shows the current/voltagecharacteristic of the ferroelectric single electron transistor memory ofthe invention. The operations of the first to third embodiments arebasically similar.

A characteristic inherent to the single electron transistor is that acurrent between the source 1 and the drain 2 can be read based on a halfof electron. In the single electron transistor, an electrostaticcapacitance C is very small, and the number of digit of theelectrostatic capacitance C approaches that of electron charges. When agate voltage is fixed, a current/voltage characteristic between thesource 1 and the drain 2 is stepped, and proportional and constantstates are repeated to increase a current value. In this state, itcannot be determined whether reading based on the unit of electron isnow being carried out or not. Accordingly, the gate voltage is changed.In this case, a potential between the source 1 and the drain 2 ismaintained constant.

By changing a gate potential, a current between the source 1 and thedrain 2 can be controlled. In other words, the gate potential can causea current to flow between the source 1 and the drain 2 (High state inFIG. 7), and the gate potential can also prevent the flowing of currentbetween the source 1 and the drain 2 (Low state in FIG. 7). The numbersof High and Low states are correspondent to quantized levels in theisland electrode 3. In this way, by gate potential sweeping, High (on)and Low (off) sates are determined.

In the case of the invention, a voltage applied to the gate 7 causesgate sweeping to be carried out at a stretch up to a predetermined fixedpotential by charges stored in the ferroelectric layer 6. However, inthe case of the invention, destructive reading-out occurs, and noprevious charges are stored after reading. Thus, charges can be stored(written) in the ferroelectric layer 6 by applying a new gate potentialand maintained until next reading.

With regard to a specific writing operation, first, a voltage betweenthe source 1 and the drain 2 is set equal to 0, and a voltage V_(g) isthen applied to the gate 7. When a potential V2 of the ferroelectriclayer 6 is increased equal to a coercive electric field or more,polarization occurs in the ferroelectric layer 6, and generated internalcharges Q_(g) are stored (written) as non-volatile charges. According tothe first embodiment, the electric field of the ferroelectric layer 6 isdirectly applied as a gate electric field to the island electrode 3, anda current between the source 1 and the drain 2 is controlled. On theother hand, according to each of the second and third embodiments, theamounts of internal charges Q_(g) are equal between the ferroelectriclayer 6 and the Low-k layer 12, the electric field of the Low-k layer 12is directly applied as the gate electric field to the island electrode3, and a current between the source 1 and the drain 2 is controlled.

Next, with regard to a specific reading operation, first, when a biasvoltage is applied between the source 1 and the drain 2, electrons aretunneled through the insulating layers 4 and 5, and stored in the islandelectrode 3. Electrostatic potential energy by these stored charges isquantized in the island electrode 3 of an nm scale. Accordingly, acurrent I_(sd) observed between the source 1 and the drain 2 iscyclically changed with respect to the gate potential by reflecting thequantized energy. The cyclical waveform of the current I_(sd) betweenthe source 1 and the drain 2 with respect to the gate potential becomesone like that shown in FIG. 7. Stored information 0 (Low) or 1 (High)can be read in accordance with the gate potential corresponding to theinternal charges Q_(g) induced during the writing operation. For thedetermination of 0 or 1, the number of read cycle peaks may becorresponded ) to 0 or 1. If a noise level is low, multiple values maybe stored by corresponding to individual peaks. In this case, with agate voltage=e/2C_(g) equivalent in principle to “e/2” set as a minimumunit, the current I_(sd) between the source 1 and the drain 2 can bemeasured, making it possible to carry out reading with high sensitivity.

An erasing operation is carried out by applying to a gate 7 a voltagereverse to the voltage thereto during the writing operation.

The single electron transistor memory has mainly been described. Itshould be understood, however, that the invention could be applied toother non-volatile memories.

INDUSTRIAL APPLICAPABILITY

According to the invention, as described above, a ferroelectric layer isused for the gate portion, and a device operation is realized, where thephenomenon of tunneling of charges through the insulating film isprevented. Thus, it is possible to achieve high device reliability,reduce power consumption, and realize a high-speed operation.

More specifically, the invention is advantageous in the followingrespects:

By using the polarization of the ferroelectric layer as memorywriting/erasing means, a high-speed operation can be performed at thepolarization response of an atomic order.

By using the single electron transistor for charge reading, an operationcan be performed by very small charges and at low power consumption.

Since the necessity of tunneling a current through the gate insulatingfilm is eliminated, high durability (mainly decided by the durability ofthe ferroelectric layer) can be provided, and a device size can be madevery small.

By using the established semiconductor manufacturing method (3-layerresist and 3-angle Al deposition (see Jpn. J. Appl. Phys. 35, 1465(1996) by Y. Nakamura et al.), or the like), the precise control of theinsulating film (thickness direction/horizontal direction) is madeunnecessary, and the quality of a deposited Al electrode is difficult tobe affected by the layered surface. Accordingly, the manufacturingprocess can be facilitated and simplified compared with the Siferroelectric memory process.

By providing the Low-k layer (SiO₂) as the gate layer structure, theincrease of a gate capacity caused by the high dielectric constant ofthe ferroelectric film can be screened.

By using the growth of a ferroelectric layer on the lower gate metalelectrode, the flatness/crystallinity of the ferroelectric layer can beenhanced.

By providing the diffusion barrier layer, the thermal diffusion of theferroelectric component to Si can be prevented in the heat treatmentprocess of the ferroelectric layer.

By employing the layered structure, the degree of device integration canbe increased.

What is claimed is:
 1. A non-volatile memory comprising: a singleelectron transistor having a gate, a ferroelectric layer on said gate,and an island electrode on said ferroelectric layer opposite said gate,said island electrode being held between a source and a drain byinterpolating insulating layers that are between the island electrodeand each of the source and the drain, said island electrode beingelectrically switched by a change of polarization of said ferroelectriclayer caused by application of a charge as small as ½ electron to saidgate.
 2. A non-volatile memory comprising: a gate; a ferroelectric layerdisposed on said gate; a Low-k layer disposed on said ferroelectriclayer; and an island electrode disposed on said Low-k layer, heldbetween a source and a drain by interpolating insulating layers betweenthe island electrode and each of the source and the drain, andelectrically connected to said gate.
 3. Anon-volatile memory comprising:a gate; a ferroelectric layer disposed on said gate; an upper gatedisposed on said ferroelectric layer; a Low-k layer disposed on saidferroelectric layer; and an island electrode disposed on said Low-klayer, held between a source and a drain by interpolating insulatinglayers between the island electrode and each of the source and thedrain, and electrically connected to said gate.
 4. A non-volatile memoryaccording to claim 3, wherein said ferroelectric layer includes aperovskite phase portion formed on said gate, and a pyrochlore phaseportion formed on a portion other than said gate.
 5. A non-volatilememory according to claim 1, further comprising a diffusion barrierlayer formed on a substrate, wherein said gate is disposed on saiddiffusion layer.
 6. A non-volatile memory according to claim 5, whereinsaid diffusion barrier layer has a TiO_(x) film thickness substantiallyset equal to 20 nm, alternatively higher.
 7. A non-volatile memoryaccording to claim 1, wherein said gate is made of one selected from Ptand RhO_(x).
 8. A non-volatile memory according to claim 1, wherein saidferroelectric layer is made of one selected from PbTiO₃,PbZr_(x)Ti_(1−x)O₃, (Pb,Sr)TiO₃, (Pb_(1−y)Sr_(y))(Ti¹⁻) Zr_(x)O₃,SrBi₂Ta₂O₉, BaTiO₃, Bi₃Ti₄O₁₂, LiNbO₃, and SrBi₂Ta_(x)Nb¹⁻O₉.
 9. Anon-volatile memory according to claim 2, wherein said Low-k layer ismade of one selected from SiO₂ and Si₃N₄.
 10. A non-volatile memoryaccording to claim 2, wherein said ferroelectric layer is made of oneselected from PbZr_(x)T_(1−x), and (Pb_(1−y)Sr_(y))(Ti_(1−x))ZrxO₃, andhas a thickness set substantially equal to about 100 nm, and said Low-klayer is made of one selected from SiO₂ and Si₃N₄, and has a thicknessset substantially equal to 10 nm, alternatively lower.
 11. Anon-volatile memory according to claim 2, wherein said ferroelectriclayer is made of SrBi₂Ta₂O₉, and has a thickness set substantially equalto about 200 nm, and said Low-k layer is made of one selected from SiO₂and Si₃N₄, and has a thickness set substantially equal to 20 nm,alternatively lower.
 12. A non-volatile memory according to claim 1,wherein said island electrode, said source and said drain are made ofone of Al and Ti.
 13. A non-volatile memory according to claim 1,wherein said ferroelectric layer is brought into contact with saidisland electrode, said source and said drain and with said gate and saiddiffusion barrier layer around said gate.
 14. A non-volatile memoryaccording to claim 2, further comprising a diffusion barrier layerformed on a substrate, wherein said gate is disposed on said diffusionlayer.
 15. A non-volatile memory according to claim 14, wherein saiddiffusion barrier layer has a TiO_(x) film thickness substantially setequal to 20 nm, alternatively higher.
 16. A non-volatile memoryaccording to claim 2, wherein said gate is made of one selected from Ptand Rho_(x).
 17. A non-volatile memory according to claim 2, whereinsaid ferroelectric layer is made of one selected from PbTiO₃,PbZr_(x)Ti_(1−x)O₃, (Pb,Sr)TiO₃, (Pb_(1−y)Sr_(y))(Ti_(1−x)) Zr_(x)O₃,SrBi₂Ta₂O₉, BaTiO₃, Bi₃Ti₄O₁₂, LiNbO₃, and SrBi₂Ta_(x)Nb_(1−x)O₉.
 18. Anon-volatile memory according to claim 2, wherein said island electrode,said source and said drain are made of one of Al and Ti.
 19. Anon-volatile memory according to claim 2, wherein said ferroelectriclayer is brought into contact with said island electrode, said sourceand said drain and with said gate and said diffusion barrier layeraround said gate.
 20. A non-volatile memory according to claim 3,further comprising a diffusion barrier layer formed on a substrate,wherein said gate is disposed on said diffusion layer.
 21. Anon-volatile memory according to claim 20, wherein said diffusionbarrier layer has a TiO_(x) film thickness substantially set equal to 20nm, alternatively higher.
 22. A non-volatile memory according to claim3, wherein said gate is made of one selected from Pt and Rho_(x).
 23. Anon-volatile memory according to claim 3, wherein said ferroelectriclayer is made of one selected from PbTiO₃, PbZr_(x)Ti_(1−x)O₃,(Pb,Sr)TiO₃, (Pb_(1−y)Sr_(y)) (Ti_(1−x)) Zr_(x)O₃, SrBi₂Ta₂O₉, BaTiO₃,Bi₃Ti₄O₁₂, LiNbO₃, and SrBi₂Ta_(x)Nb_(1−x)O₉.
 24. A non-volatile memoryaccording to claim 3, wherein said Low-k layer is made of one selectedfrom SiO₂ and Si₃N₄.
 25. A non-volatile memory according to claim 3,wherein said ferroelectric layer is made of one selected fromPbZr_(x)T_(1−x), and (Pb_(1−y)Sr_(y))(Ti_(1−x)) ZrxO₃, and has athickness set substantially equal to about 100 nm, and said Low-k layeris made of one selected from SiO₂ and Si₃N₄, and has a thickness setsubstantially equal to 10 nm, alternatively lower.
 26. A non-volatilememory according to claim 3, wherein said ferroelectric layer is made ofSrBi₂Ta₂O₉, and has a thickness set substantially equal to about 200 nm,and said Low-k layer is made of one selected from SiO₂ and Si₃N₄, andhas a thickness set substantially equal to 20 nm, alternatively lower.27. A non-volatile memory according to claim 3, wherein said islandelectrode, said source and said drain are made of Al, alternatively Ti.28. A non-volatile memory according to claim 3, wherein saidferroelectric layer is brought into contact with said island electrode,said source and said drain and with said gate and said diffusion barrierlayer around said gate.
 29. The non-volatile memory of claim 1, furthercomprising a Low-k layer between said island electrode and saidferroelectric layer.
 30. The non-volatile memory of claim 29, furthercomprising an upper gate directly on said ferroelectric layer adjacentto said Low-k layer.